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MPG HLL Electronics

 

 

   
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  The need for bigger and faster multi channel X-ray detectors generates ever growing amounts of data. Deploying modern integrated electronics is required to build an adequate data acquisition system. It has to control the detector, to process analog data, to convert the analog signals into digital values and store data in computer memory. Algorithms are working on raw data and generating real images and spectra. A challenging part of data acquisition is the extraction of an information signal from a noisy detector output which is usually carried out by analog filtering stages integrated in one silicon chip.   Schematic of the three
Figure A
Schematic drawing of the three pillars of electronics. DAQ Data Aquisition System ASIC Application Specic Integrated Circuit PCB Printed Circuit Board 16 MPG HLL.
   
         
  To combine the various components of electronics sophisticated printed circuit boards and delicate mountings are necessary. We improve our detector developments by the design of readout electronics. In cooperation with partners the MPG HLL integrates complex working detector systems.    
       
  Electronics development is performed in three sections: DAQ, ASIC and PCB. The DAQ (Data Acquisition) system controls the detector readout cycles and moves the measured data to a computer memory where it can be analyzed or stored on hard disk. DAQ design builds complete systems involving standard consumer computer technology, e.g. cPCI. Hence we can benefit from increasing processing power, higher bus bandwidth and cheaper memory.    
           
  This technology is easy to use and proven to work reliably. But DAQ design is more than just computers. The readout scheme is often ruled by the detector type and the related application resulting in a variety of demands: For example, signals can be stored in the detector and therefore the readout can be organized in specific time slices (synchronous readout). Or the signals have to be transferred in the very moment they arrive in the detector. How are ASICs to be placed and controlled – by bus architecture or by means of point-to-point connections? Also, power supply and power sequencing is a big issue in the field of state-of-the-art measuring detector systems.   Photo of a pnCCD controller and data acquisition system
Figure B
Photo of a pnCCD controller and data acquisition system.
   
       
  A typical pnCCD readout system consists of
  • Computer – for data processing & visualization
  • Sequencer (SEQ) – the master clock, it produces clocks and communication signals for the front end ASICs and the other system parts
  • Analog digital converters (ADCs) – these convert the mostly analog output values of the readout ASICs to digital values the computer can process
  • PCB – the PCBs are located inside and outside the vacuum providing the basis for the detector hybrid
  • Detector hybrid – this PCB holds the detector and front endASICs
  • Power supply – generates and measures the needed voltages or currents for detector, ASICs and PCBs
   
       
  ASIC stands for: Application Specific Integrated Circuit, meaning microelectronic chips. To readout multi-channel silicon detectors the use of monolithic integrated circuits is mandatory. In high-energy physics experiments and astronomical applications the number of the required detection channels is constantly increasing. Charge Coupled Devices (CCDs) and Active Pixel Sensors (APS) with more than 106 elements have been developed and produced. Incorporating many channels on the detectors increases the complexity of the system, but the provided parallelism gives the advantage of having more time to process the output signals allowing low-noise as well as high-rate readout.    
       
  A variety of ASICs is necessary for the correct operation and read-out of these detectors: At first they should provide the right biasing conditions and control signals for the detector elements, like the charge transfer signals for the CCD and the reset trigger for the APS matrices. Then the integrated front-end electronics should be able to process the signals coming from the detector maximizing the signal-tonoise ratio, satisfying at the same time the severe requirements in terms of speed and power consumption, dictated by different experimental constraints.    
       
  A variety of ASICs is necessary for the correct operation and read-out of these detectors: At first they should provide the right biasing conditions and control signals for the detector elements, like the charge transfer signals for the CCD and the reset trigger for the APS matrices. Then the integrated front-end electronics should be able to process the signals coming from the detector maximizing the signal-tonoise ratio, satisfying at the same time the severe requirements in terms of speed and power consumption, dictated by different experimental constraints. In this sense the small area of integrated circuits is of advantage: First it allows the processing of a large amount of channels and it provides signal amplification and filtering as close as possible to the detector.   Close-up view of a CAMEX wafer
Figure C
Close-up view of a CAMEX wafer. Each die performs pre-amplification, signal processing and multiplexing of a block of 128 CCD channels.
   
           
  In this way it avoids transmitting small signals over long connections. This in turn would increase the capacitive load that can be affected by additional noise sources and pickups.    
       
  It is a challenging task to design low-noise, highly integrated, low-power and high speed electronics suitable to cope with the striking properties of the newest silicon detectors produced at MPG HLL (pnCCDs, DePMOS matrices and SDD arrays). For this reason MPG HLL is putting a growing effort in the development of ASICs. In collaboration with other research institutes, the MPG HLL invests in the research of new architectures and design solutions for CMOS digital, analog and mixed-signal custom ASICs. They all provide low noise, high speed and flexible readout options for a large variety of the detectors.    
       
  ASIC production focuses the following structures:
  • Low noise amplifiers
  • Low noise switchers
  • Analog time variant and time invariant shaping amplifiers
  • Digital and analog memory cells
  • Digital and analog multiplexers.
The ASICs are produced in different commercially available CMOS, JFET-CMOS and BiCMOS technologies.
  Photo of a field programmable gate array (FPGA) used in our DEPFET data acquisition system
Figure D
Photo of a field programmable gate array (FPGA) used in our DEPFET data acquisition system. The reprogrammable hardware performs sequencing and housekeeping of the detector readout.
   
       
  PCB (printed circuit board) technology is needed for merging all these components. With the increasing demand for higher speed, higher channel-density and lower noise, interconnection gets more and more complicated. Our development process employs modern PCB design software, sending PCB design files to foundries where the plain PCB is manufactured. Mounting bonding and solder work even for highly integrated devices, e.g. ball grid arrays (BGAs), is accomplished in our facilities at MPG HLL or MPE.    
       
  The need for PCBs operated in vacuum and heavily cooled (−130 °C) environments remains a major challenge for our laboratory: We currently use aluminum oxide ceramics manufactured in a five layer thick film hybrid technology using silk screen printing. We adapted this common technology for our needs in co-operation with the MPP.    
       
  Further improvements in integrated circuits will increase integration density and improve readout speed or noise. The ongoing trend in computer technology will give us the tools for handling data rates generated by new generations of detectors. With our data acquisition systems assisting the development of future detectors, the MPG HLL faces requirements of future missions, e.g.
To internal topicXEUS, To internal topicILC and To internal topicSIMBOL-X as well as To internal topicBepiColombo.
   
       
   
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Photo of a field programmable
gate array (FPGA) used in our
DEPFET data acquisition system.