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  Technology  
        
             
  Though our technology has its origin in microelectronics, our fabrication process differs substantially from microelectronics standards. Purity reasons, the demand for a fully doublesided process as well as large detector surfaces are the main causes making our fabrication process neither adaptable nor directly transferable into a conventional microelectronics process unit.    
             
  We are in the unique position to have a production line which combines processes for ultra-pure silicon wafers with the small-scale technology of very large system integration (VLSI) electronics. Except ion implantation which is outsourced to service providers, processing is done exclusively in our 1,000 square meter cleanroom. A variety of technology key features distinguishes the MPG HLL from microelectronics fabrication.   Cleanroom wet chemistry section  
             
 
  Electronics and Design on a Single - Wafer
         
 
  The combination of detector and electronics design on a single wafer allows the integration of signal amplification stages into the radiation sensor by either “classic” JFETs (figure on the right) and MOSFETs or more recent developed DEPFETs (To internal topicDEPFET Active Pixel Sensors). The advantage of this is a minimized readout capacitance for lower noise levels even at very high readout speeds as well as reduced sensitivity to microphony and electrical interference.   Readout node of a finished pnCCD chip with an on-chip SSJFET transistor
         
  Radiation Entrance Window
         
  The radiation entrance window is also one of the key features for the detection of low energy photons and particles. The dead layer has to be as thin as possible, but at the same time has to stand a sufficient radiation dose for a long lifetime of the detectors. The entrance window can also be tailored to optimize the transmission or suppression of certain wavelengths ranges. For detection of optical wavelengths, antireflective coatings are formed by stacked dielectric layers of appropriate thickness.
 
           
  Leakage Current
           
             
  The leakage current of our devices is another critical parameter for photon energy measurement because its variation cannot be distinguished from the signal. Impurities in the bulk material introduced during processing are the main reasons for leakage current.   Wafer boats containing wafers to be inse
   
   
  Oxidation  
  The starting material for wafer production is detector grade float zone silicon of high resistivity with a diameter of 150 mm and a thickness of 450 µm. At the beginning of processing a thin oxide layer is grown on the surface of the silicon wafer (figure to the right).  
         
  The quality of this oxide defines the boundary of the silicon crystal and many properties of MOS structures. The cleanliness of this very first processing step has also a strong influence on the final detectors.
           
 

Fully Double-Sided Process

           
  In our radiation detectors both sides of the wafers will be used – the front side for readout electronics and the back side as radiation entrance window. So it is a MPG HLL special requirement to find a process sequence compatible with both sides.
 
 
  Production Cycle – A Selection
 
 
  Our entire fabrication consists of up to 500 individual steps. They are repeated as often as needed to deliver total defect free circuits. In this our production cycle differs also significantly from microelectronics fabrication – and will be described as follows:
   
  Ion implantation
   
  Ion implantation is used to define pn–junctions and to shape the electric potential inside the wafer. The potential defines the single electron’s path inside the silicon volume and (via Ramo’s Theorem) the induced signal at the readout nodes. The energy of the implant corresponds to a depth of the maximum dose of several nanometers up to about some micrometers.
   
  Insulating Layers
   
  We use different dielectrics as insulating layers. These thin layers with a thickness varying between several nanometers and some micrometers, are deposited in a furnace by low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).
   
  Photolithography    
       
  While the depth of the implant is controlled by ion energy, the lateral extend is defined by masking with photoresist. The photoresist is spun on the wafer surface and then exposed to UV-light making the resist dissolvable in a developer solution. The exposure is done either through a mask by means of proximity projection, or with a direct writing laser system. Despite its slower speed, direct writing of the design data with the laser is usually preferred, as it allows smaller feature sizes down to 1,5 µm and faster design changes.   Photoresist layer after exposure and development
   
  The use of projection lithography (wafer stepper) is prohibited by the large dimension of the sensors. The figure above on the right shows a photoresist layer after development. After photolithography, the pattern can also be transferred into the layer on which the resist is coated by wet chemical etching.
   
  Conductive Layers
       
  Polysilicon is also deposited in the LPCVD furnace. It is used as conductor withstanding much higher temperature during later processing steps but not offering the same low resistivity as aluminum. In addition, polysilicon can be covered with a self–aligned isolator that is grown from the silicon by wet oxidation in water vapor. Aluminum is used as a conductor between silicon and the outside world. Aluminum is deposited by sputtering off a high purity aluminum plate and forming a low resistive ohmic contact.   A DEPFET pixel cell
       
  The sputtering process creates also radiation damage in the silicon bulk which can be healed by consecutive tempering. Currently our technology offers a maximum of two polysilicon and two aluminum layers per side. These four layers are necessary for the To internal topic DEPFET Active Pixel Sensors (figure above on the right).
       
  Passivation Layer Applicationon    
       
  Before the wafers have left the cleanroom area, a passivation layer made of synthetic material is applied for easy mounting and reduced sensitivity to particles. The plastic is spun like photoresist and is photosensitive so that it can be selectively hardened by UV–exposure. The passivation layer as well as the whole sensor has been tested to withstand temperatures between liquid nitroge and several hundred degrees Celsius.
       
  Inline Control Quality Management    
       
  All process steps from selecting wafer material to final cleaning on wafer level are constantly checked and documented. We use detailed machine logging, a wafer database and several analysis methods (REM, SIMS, VPD, various electrical tests, control of airand water purification) to ensure quality. Another challenging effort is to inspect all lithographic and structuring steps by microscope.We are screening the whole wafer surface to find lithographic artifacts and defects. Although we have established several methods to repair some of them, sometimes complete lithography steps have to b repeated. Only such a kind of high inspection effort is ensuring a high yield through many processing steps with extremely large devices up to 100 cm².
       
  Electrical Wafer-Level Testing    
       
  Intensive inline and offline electricaltesting is performed at wafer level. Electrical contacts, insulator properties and resistor values are measured. Device parameters like leakage currents, flatband shift or depletion voltages are determined.
       
  With a custom made liquid nitrogen cooled probe test instrument (figure on the right) even spectral performanceat various operating temperatures (from RT to −100 °C) is tested. A pre-selection of flight devices is possible on wafer level before dicing, mounting and bonding.  
       
  Dicing – Mounting – Bonding    
       
  After measurements on wafer level we separate the wafer into chips. The diced chips are cleaned and mounted on dedicated ceramic carriers. The mounted chips are bonded (figure on the right) by an automatic or manual bonding tool. Wafer bonding techniques as well as novel chip and wafer soldering processes are currently under study.  
       
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